As a conventional memory control method, in the case in which memory access requests given from a plurality of masters conflict with each other in an information processing device constituted by a CPU (central calculating circuit) and the other masters for accessing a memory, and the memory, for example, a processing is carried out in accordance with priority of the memory access requests. In such a memory control method, there has been known a technique for switching an access right for accessing a DRAM to transfer data in such a manner that the data of a control circuit on a host computer side to be a master for accessing a memory and a control circuit FIFO memory on a hard disk device side do not cause an overflow or an underflow (see Patent Document 1, for example).
As a memory control method of an information processing device constituted by a CPU, a liquid crystal display device and a CRT display device which are masters for accessing a memory, and the memory, moreover, there has been known a technique for giving priority to access a CPU to a DRAM and transferring data in such a manner that the data of an FIFO memory for a liquid crystal display which is provided with the CRT display device do not cause an overflow or an underflow (see Patent Document 2, for example).
As a memory control method of an information processing device constituted by a CPU and a DMA device which are masters for accessing a memory, and the memory, furthermore, there has been known a technique for giving priority to access the CPU to the DRAM and transferring data in such a manner that the data of an FIFO memory provided in the DMA device do not cause an overflow or an underflow (see Patent Document 3).    [Patent Document 1] JP-A-9-231158 Publication    [Patent Document 2] JP-A-2000-35778 Publication    [Patent Document 3] JP-A-2000-315187 Publication